Wire bonding is a well-known die packaging method that electrically connects a semiconductor die to the finger leads of a packaging substrate. As shown in FIGS. 1 and 2, a packaging substrate 10 is used to package a semiconductor die 20. The semiconductor die 20 rests face up upon the packaging substrate 10, and comprises a plurality of pads 22. The packaging substrate 10 includes a plurality of lead fingers or traces 12, which surround the die 20, and which terminate in what are generally called bond fingers or wedges 14. The wedges 14, via the traces 12, electrically connect to a plurality of pins, contacts, solder balls or the like (not shown) on the external surface of the packaging substrate 10 to provide electrical contact with external circuitry. Electrically connecting the pads 22 with the wedges 14 are a plurality of bond wires 30. Typically, there is a one-to-one correspondence between wedges 14 and pads 22, but this is certainly not a requirement, particularly in the case where the wedges 14 form a ground or power ring, or similar structure, around the die 20.
A wire bonding apparatus extrudes the bond wires 30, creating a ball bond 32 upon the pads 22, and a stitch bond 34 upon the wedges 14. The wire bonding apparatus can control both the loop height h of the bond wire 30, which is the height the bond wire 30 rises above the top surface of the substrate 10, and can also control the flat length f of the bond wire 30, which is the distance from the ball bond 32 to a bend 33 in the bond wire 30 at which the bond wire 30 begins to descend towards the substrate 10 for the wedge 14.
To provide sufficient tolerances for the wire bonding apparatus, the pads 22 should have certain minimum dimensions, which may be as little as 35 μm. Typical pad 22 sizes, however, range from 52 μm to 65 μm, and the pads 22 are generally square, although rectangular die pads are also possible. Typical pitch widths are 70 μm, with trends towards smaller pitch widths, such as 65 μm and lower as equipment and processes develop. The semiconductor die 20 includes circuitry 28 that electrically connects to the pads 22. Some applications will require that the circuitry 28 utilize a large number of pads 22 for input/output (I/O), power connections and the like. If, as shown in FIG. 1, a single row, or tier, of pads 22 is used around the circumference of the die 20, the minimum pitch widths of the pads 22 will force a total minimum size upon the die 20 to accommodate the pads 22. Semiconductor real estate on the die 20, however, is relatively expensive. Manufacturing costs of semiconductor devices can be significantly reduced if a bare minimum of semiconductor area is used for the die 20. Hence, as shown in FIG. 3, multi-rowed pads are now quite common.
As shown in FIG. 3, a semiconductor die 40 may include a plurality of pads 42 that are arranged in an outer row 44 and an inner row 46. Wedges 52 surround the die 40, and electrically connect to the pads 42 by way of bond wires 60. The wedges 52 may similarly be arranged in a series of concentric rings or rows, having an inner row 54 and an outer row 56 of wedges 52. By providing inner 46 and outer 44 rows of pads 42, a significant savings in semiconductor real estate on the die 40 is made possible. To avoid shorting between the various bond wires 60, the wedges 52 and pads 42 are arranged so that the outer row pads 44 are wire bonded to the inner row wedges 54, and the inner row pads 46 are wire bonded to the outer row wedges 56. As shown in FIG. 4, the loop height of the bond wire 60 that connects the outer row wedges 56 to the inner row pads 46 is relatively high; because of this height, such bond wires 60 are termed upper tier wires 66. Similarly, the bonding wire 60 that connects the outer row pads 44 to the inner row wedges 54 has a relatively low loop height, and is thus called a lower tier bonding wire 64. Because the row position of a pad 42 will in large part determine the loop height of its corresponding bond wire 60, pads 42 may be spoken of as lower tier pads 44 (i.e., those that are outermost with respect to the circuitry 48), and upper tier pads 46 (i.e., those that lie closest in to the circuitry 48). A similar terminology may be employed with the wedges 52 for the same reason. Lower tier pads 44 and wedges 54 are generally used for power and ground connections, while the upper tier pads 46 and wedges 56 are used for I/O connections. This electrical arrangement is not a physical requirement, but rather is considered an electrical “best practice,” as short power-related bond wires 60 tend to improve the electrical performance of the entire package.
Wire bonding is a well-developed technology, and is considerably cheaper to use than the so-called flip-chip packaging method, in which the die is bonded face-down onto the substrate, with the pads on the die electrically contacting the substrate wedges without any intervening wires. For example, what may cost three to four dollars to package using wire bonding can cost upwards of ten to fifteen dollars using flip-chip. Flip-chip, however, is preferred in high-frequency applications, because of crosstalk that can develop between wire bonds. Indeed, flip-chip packaging is the preferred technology for signals in the 2 GHz or above range. As such, high-frequency devices tend to be relatively expensive. It would therefore be desirable to find a method, and related packaging system, that enables the use of wire bonding in high-frequency applications, particularly in applications involving signals of 2 GHz or greater.